mirror of https://github.com/YosysHQ/yosys.git
417 lines
8.1 KiB
C++
417 lines
8.1 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef SIGTOOLS_H
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#define SIGTOOLS_H
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#include "kernel/yosys.h"
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YOSYS_NAMESPACE_BEGIN
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struct SigPool
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{
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struct bitDef_t : public std::pair<RTLIL::Wire*, int> {
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bitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }
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bitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }
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};
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std::set<bitDef_t> bits;
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void clear()
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{
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bits.clear();
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}
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void add(RTLIL::SigSpec sig)
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{
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for (auto &bit : sig)
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if (bit.wire != NULL)
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bits.insert(bit);
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}
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void add(const SigPool &other)
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{
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for (auto &bit : other.bits)
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bits.insert(bit);
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}
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void del(RTLIL::SigSpec sig)
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{
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for (auto &bit : sig)
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if (bit.wire != NULL)
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bits.erase(bit);
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}
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void del(const SigPool &other)
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{
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for (auto &bit : other.bits)
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bits.erase(bit);
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}
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void expand(RTLIL::SigSpec from, RTLIL::SigSpec to)
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{
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log_assert(SIZE(from) == SIZE(to));
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for (int i = 0; i < SIZE(from); i++) {
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bitDef_t bit_from(from[i]), bit_to(to[i]);
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if (bit_from.first != NULL && bit_to.first != NULL && bits.count(bit_from) > 0)
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bits.insert(bit_to);
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}
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}
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RTLIL::SigSpec extract(RTLIL::SigSpec sig)
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{
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RTLIL::SigSpec result;
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for (auto &bit : sig)
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if (bit.wire != NULL && bits.count(bit))
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result.append_bit(bit);
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return result;
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}
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RTLIL::SigSpec remove(RTLIL::SigSpec sig)
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{
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RTLIL::SigSpec result;
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for (auto &bit : sig)
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if (bit.wire != NULL && bits.count(bit) == 0)
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result.append(bit);
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return result;
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}
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bool check(RTLIL::SigBit bit)
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{
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return bit.wire != NULL && bits.count(bit);
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}
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bool check_any(RTLIL::SigSpec sig)
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{
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for (auto &bit : sig)
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if (bit.wire != NULL && bits.count(bit))
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return true;
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return false;
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}
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bool check_all(RTLIL::SigSpec sig)
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{
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for (auto &bit : sig)
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if (bit.wire != NULL && bits.count(bit) == 0)
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return false;
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return true;
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}
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RTLIL::SigSpec export_one()
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{
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for (auto &bit : bits)
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return RTLIL::SigSpec(bit.first, bit.second);
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return RTLIL::SigSpec();
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}
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RTLIL::SigSpec export_all()
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{
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std::set<RTLIL::SigBit> sig;
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for (auto &bit : bits)
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sig.insert(RTLIL::SigBit(bit.first, bit.second));
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return sig;
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}
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size_t size()
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{
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return bits.size();
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}
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};
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template <typename T, class Compare = std::less<T>>
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struct SigSet
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{
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struct bitDef_t : public std::pair<RTLIL::Wire*, int> {
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bitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }
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bitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }
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};
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std::map<bitDef_t, std::set<T, Compare>> bits;
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void clear()
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{
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bits.clear();
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}
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void insert(RTLIL::SigSpec sig, T data)
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{
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for (auto &bit : sig)
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if (bit.wire != NULL)
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bits[bit].insert(data);
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}
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void insert(RTLIL::SigSpec sig, const std::set<T> &data)
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{
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for (auto &bit : sig)
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if (bit.wire != NULL)
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bits[bit].insert(data.begin(), data.end());
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}
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void erase(RTLIL::SigSpec sig)
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{
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for (auto &bit : sig)
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if (bit.wire != NULL)
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bits[bit].clear();
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}
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void erase(RTLIL::SigSpec sig, T data)
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{
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for (auto &bit : sig)
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if (bit.wire != NULL)
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bits[bit].erase(data);
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}
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void erase(RTLIL::SigSpec sig, const std::set<T> &data)
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{
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for (auto &bit : sig)
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if (bit.wire != NULL)
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bits[bit].erase(data.begin(), data.end());
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}
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void find(RTLIL::SigSpec sig, std::set<T> &result)
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{
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for (auto &bit : sig)
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if (bit.wire != NULL) {
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auto &data = bits[bit];
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result.insert(data.begin(), data.end());
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}
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}
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std::set<T> find(RTLIL::SigSpec sig)
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{
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std::set<T> result;
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find(sig, result);
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return result;
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}
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bool has(RTLIL::SigSpec sig)
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{
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for (auto &bit : sig)
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if (bit.wire != NULL && bits.count(bit))
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return true;
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return false;
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}
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};
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struct SigMap
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{
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struct bitDef_t : public std::pair<RTLIL::Wire*, int> {
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bitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }
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bitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }
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};
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struct shared_bit_data_t {
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RTLIL::SigBit map_to;
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std::set<bitDef_t> bits;
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};
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std::map<bitDef_t, shared_bit_data_t*> bits;
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SigMap(RTLIL::Module *module = NULL)
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{
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if (module != NULL)
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set(module);
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}
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SigMap(const SigMap &other)
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{
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copy(other);
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}
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const SigMap &operator=(const SigMap &other)
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{
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copy(other);
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return *this;
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}
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void copy(const SigMap &other)
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{
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clear();
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for (auto &bit : other.bits) {
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bits[bit.first] = new shared_bit_data_t;
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bits[bit.first]->map_to = bit.second->map_to;
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bits[bit.first]->bits = bit.second->bits;
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}
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}
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void swap(SigMap &other)
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{
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bits.swap(other.bits);
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}
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~SigMap()
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{
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clear();
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}
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void clear()
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{
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std::set<shared_bit_data_t*> all_bd_ptr;
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for (auto &it : bits)
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all_bd_ptr.insert(it.second);
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for (auto bd_ptr : all_bd_ptr)
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delete bd_ptr;
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bits.clear();
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}
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void set(RTLIL::Module *module)
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{
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clear();
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for (auto &it : module->connections())
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add(it.first, it.second);
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}
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// internal helper function
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void register_bit(const RTLIL::SigBit &bit)
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{
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if (bit.wire && bits.count(bit) == 0) {
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shared_bit_data_t *bd = new shared_bit_data_t;
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bd->map_to = bit;
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bd->bits.insert(bit);
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bits[bit] = bd;
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}
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}
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// internal helper function
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void unregister_bit(const RTLIL::SigBit &bit)
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{
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if (bit.wire && bits.count(bit) > 0) {
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shared_bit_data_t *bd = bits[bit];
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bd->bits.erase(bit);
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if (bd->bits.size() == 0)
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delete bd;
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bits.erase(bit);
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}
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}
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// internal helper function
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void merge_bit(const RTLIL::SigBit &bit1, const RTLIL::SigBit &bit2)
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{
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log_assert(bit1.wire != NULL && bit2.wire != NULL);
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shared_bit_data_t *bd1 = bits[bit1];
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shared_bit_data_t *bd2 = bits[bit2];
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log_assert(bd1 != NULL && bd2 != NULL);
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if (bd1 == bd2)
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return;
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if (bd1->bits.size() < bd2->bits.size())
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{
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for (auto &bit : bd1->bits)
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bits[bit] = bd2;
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bd2->bits.insert(bd1->bits.begin(), bd1->bits.end());
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delete bd1;
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}
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else
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{
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bd1->map_to = bd2->map_to;
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for (auto &bit : bd2->bits)
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bits[bit] = bd1;
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bd1->bits.insert(bd2->bits.begin(), bd2->bits.end());
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delete bd2;
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}
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}
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// internal helper function
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void set_bit(const RTLIL::SigBit &bit1, const RTLIL::SigBit &bit2)
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{
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log_assert(bit1.wire != NULL);
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log_assert(bits.count(bit1) > 0);
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bits[bit1]->map_to = bit2;
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}
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// internal helper function
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void map_bit(RTLIL::SigBit &bit) const
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{
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if (bit.wire && bits.count(bit) > 0)
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bit = bits.at(bit)->map_to;
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}
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void add(RTLIL::SigSpec from, RTLIL::SigSpec to)
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{
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log_assert(SIZE(from) == SIZE(to));
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for (int i = 0; i < SIZE(from); i++)
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{
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RTLIL::SigBit &bf = from[i];
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RTLIL::SigBit &bt = to[i];
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if (bf.wire == NULL)
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continue;
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register_bit(bf);
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register_bit(bt);
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if (bt.wire != NULL)
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merge_bit(bf, bt);
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else
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set_bit(bf, bt);
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}
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}
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void add(RTLIL::SigSpec sig)
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{
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for (auto &bit : sig) {
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register_bit(bit);
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set_bit(bit, bit);
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}
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}
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void del(RTLIL::SigSpec sig)
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{
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for (auto &bit : sig)
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unregister_bit(bit);
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}
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void apply(RTLIL::SigBit &bit) const
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{
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map_bit(bit);
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}
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void apply(RTLIL::SigSpec &sig) const
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{
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for (auto &bit : sig)
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map_bit(bit);
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}
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RTLIL::SigBit operator()(RTLIL::SigBit bit) const
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{
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apply(bit);
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return bit;
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}
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RTLIL::SigSpec operator()(RTLIL::SigSpec sig) const
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{
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apply(sig);
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return sig;
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}
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RTLIL::SigSpec operator()(RTLIL::Wire *wire) const
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{
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RTLIL::SigSpec sig(wire);
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apply(sig);
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return sig;
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}
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};
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YOSYS_NAMESPACE_END
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#endif /* SIGTOOLS_H */
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