riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/techlibs/intel_alm
History
Eddie Hung 8fbb55f4ab synth_*: no need to explicitly read +/abc9_model.v 2020-05-14 10:33:56 -07:00
..
common intel_alm: direct LUTRAM cell instantiation 2020-05-07 21:03:13 +02:00
Makefile.inc intel_alm: direct LUTRAM cell instantiation 2020-05-07 21:03:13 +02:00
synth_intel_alm.cc synth_*: no need to explicitly read +/abc9_model.v 2020-05-14 10:33:56 -07:00