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tests
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xilinx: Test our DSP48A/DSP48A1 simulation models.
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2019-12-23 20:36:43 +01:00 |
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.gitignore
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Added support for initialized xilinx brams
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2015-04-06 17:07:10 +02:00 |
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Makefile.inc
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xilinx: Add xilinx_dffopt pass (#1557)
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2019-12-18 13:43:43 +01:00 |
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abc9_map.v
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Add RAM{32,64}M to abc9_map.v
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2019-12-20 13:41:23 -08:00 |
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abc9_model.v
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Rename abc_* names/attributes to more precisely be abc9_*
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2019-10-04 11:04:10 -07:00 |
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abc9_unmap.v
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Rename abc_* names/attributes to more precisely be abc9_*
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2019-10-04 11:04:10 -07:00 |
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abc9_xc7.box
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Rename abc_* names/attributes to more precisely be abc9_*
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2019-10-04 11:04:10 -07:00 |
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abc9_xc7.lut
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Rename abc_* names/attributes to more precisely be abc9_*
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2019-10-04 11:04:10 -07:00 |
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abc9_xc7_nowide.lut
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Rename abc_* names/attributes to more precisely be abc9_*
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2019-10-04 11:04:10 -07:00 |
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arith_map.v
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Instead of MUXCY/XORCY use CARRY4 (with timing)
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2019-05-21 16:19:45 -07:00 |
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brams_init.py
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synth_xilinx: Initial Spartan 6 block RAM inference support.
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2019-07-11 14:45:48 +02:00 |
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cells_map.v
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xilinx: Improve flip-flop handling.
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2019-12-18 13:43:43 +01:00 |
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cells_sim.v
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ifdef __ICARUS__ -> ifndef YOSYS
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2020-01-01 17:33:10 -08:00 |
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cells_xtra.py
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xilinx: Add simulation models for remaining CLB primitives.
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2019-12-19 18:04:04 +01:00 |
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cells_xtra.v
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xilinx: Add simulation models for remaining CLB primitives.
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2019-12-19 18:04:04 +01:00 |
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lut_map.v
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xilinx: Use INV instead of LUT1 when applicable
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2019-11-25 20:40:39 +01:00 |
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lutrams.txt
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Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q
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2019-12-16 10:41:13 -08:00 |
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lutrams_map.v
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Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram
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2019-12-16 12:06:47 -08:00 |
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mux_map.v
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Change synth_xilinx's -nomux to -minmuxf <int>
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2019-06-24 10:04:01 -07:00 |
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synth_xilinx.cc
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Merge pull request #1601 from YosysHQ/eddie/synth_retime
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2020-01-02 08:46:24 -08:00 |
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xc3s_mult_map.v
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xilinx: Support multiplier mapping for all families.
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2019-10-22 18:06:57 +02:00 |
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xc3sda_dsp_map.v
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xilinx_dsp: Initial DSP48A/DSP48A1 support.
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2019-12-22 20:51:14 +01:00 |
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xc4v_dsp_map.v
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xilinx: Support multiplier mapping for all families.
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2019-10-22 18:06:57 +02:00 |
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xc5v_dsp_map.v
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xilinx: Support multiplier mapping for all families.
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2019-10-22 18:06:57 +02:00 |
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xc6s_brams.txt
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synth_xilinx: Initial Spartan 6 block RAM inference support.
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2019-07-11 14:45:48 +02:00 |
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xc6s_brams_map.v
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RST -> RSTBRST for RAMB8BWER
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2019-07-29 16:05:44 -07:00 |
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xc6s_dsp_map.v
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xilinx_dsp: Initial DSP48A/DSP48A1 support.
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2019-12-22 20:51:14 +01:00 |
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xc6s_ff_map.v
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xilinx: Improve flip-flop handling.
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2019-12-18 13:43:43 +01:00 |
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xc7_brams_map.v
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synth_xilinx: Initial Spartan 6 block RAM inference support.
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2019-07-11 14:45:48 +02:00 |
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xc7_dsp_map.v
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xilinx: Support multiplier mapping for all families.
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2019-10-22 18:06:57 +02:00 |
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xc7_ff_map.v
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xilinx: Improve flip-flop handling.
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2019-12-18 13:43:43 +01:00 |
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xc7_xcu_brams.txt
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Add unconditional match blocks for force RAM
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2019-12-16 13:31:15 -08:00 |
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xcu_brams_map.v
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xilinx: Add support for UltraScale[+] BRAM mapping
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2019-10-23 11:47:37 +01:00 |
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xcu_dsp_map.v
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xilinx: Support multiplier mapping for all families.
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2019-10-22 18:06:57 +02:00 |
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xcup_urams.txt
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xilinx: Add URAM288 mapping for xcup
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2019-10-23 11:47:44 +01:00 |
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xcup_urams_map.v
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xilinx: Add URAM288 mapping for xcup
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2019-10-23 11:47:44 +01:00 |
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xilinx_dffopt.cc
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xilinx_dffopt: Keep order of LUT inputs.
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2019-12-19 18:01:43 +01:00 |
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