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Marcin Kościelnicki aff6ad1ce0 xilinx: Improve flip-flop handling. 
This adds support for infering more kinds of flip-flops:

- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable

Some passes have been moved (and some added) in order for dff2dffs to
work correctly.

This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities).  Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
 		2019-12-18 13:43:43 +01:00
..
tests Add pattern detection support for DSP48E1 model, check against vendor 2019-09-18 10:45:04 -07:00
.gitignore Added support for initialized xilinx brams 2015-04-06 17:07:10 +02:00
Makefile.inc synth_xilinx: Merge blackbox primitive libraries. 2019-11-06 15:11:27 +01:00
abc9_map.v abc9_map.v: fix Xilinx LUTRAM 2019-12-12 14:56:52 -08:00
abc9_model.v Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
abc9_unmap.v Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
abc9_xc7.box Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
abc9_xc7.lut Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
abc9_xc7_nowide.lut Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
arith_map.v Instead of MUXCY/XORCY use CARRY4 (with timing) 2019-05-21 16:19:45 -07:00
brams_init.py synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
cells_map.v xilinx: Improve flip-flop handling. 2019-12-18 13:43:43 +01:00
cells_sim.v RAM64M8 to also have [5:0] for address 2019-12-13 08:54:19 -08:00
cells_xtra.py xilinx: Add models for LUTRAM cells. (#1537) 2019-12-04 06:31:09 +01:00
cells_xtra.v xilinx: Add models for LUTRAM cells. (#1537) 2019-12-04 06:31:09 +01:00
lut_map.v xilinx: Use INV instead of LUT1 when applicable 2019-11-25 20:40:39 +01:00
lutrams.txt Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q 2019-12-16 10:41:13 -08:00
lutrams_map.v Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram 2019-12-16 12:06:47 -08:00
mux_map.v Change synth_xilinx's -nomux to -minmuxf <int> 2019-06-24 10:04:01 -07:00
synth_xilinx.cc xilinx: Improve flip-flop handling. 2019-12-18 13:43:43 +01:00
xc3s_mult_map.v xilinx: Support multiplier mapping for all families. 2019-10-22 18:06:57 +02:00
xc3sda_dsp_map.v xilinx: Support multiplier mapping for all families. 2019-10-22 18:06:57 +02:00
xc4v_dsp_map.v xilinx: Support multiplier mapping for all families. 2019-10-22 18:06:57 +02:00
xc5v_dsp_map.v xilinx: Support multiplier mapping for all families. 2019-10-22 18:06:57 +02:00
xc6s_brams.txt synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
xc6s_brams_map.v RST -> RSTBRST for RAMB8BWER 2019-07-29 16:05:44 -07:00
xc6s_dsp_map.v xilinx: Support multiplier mapping for all families. 2019-10-22 18:06:57 +02:00
xc6s_ff_map.v xilinx: Improve flip-flop handling. 2019-12-18 13:43:43 +01:00
xc7_brams_map.v synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
xc7_dsp_map.v xilinx: Support multiplier mapping for all families. 2019-10-22 18:06:57 +02:00
xc7_ff_map.v xilinx: Improve flip-flop handling. 2019-12-18 13:43:43 +01:00
xc7_xcu_brams.txt Add unconditional match blocks for force RAM 2019-12-16 13:31:15 -08:00
xcu_brams_map.v xilinx: Add support for UltraScale[+] BRAM mapping 2019-10-23 11:47:37 +01:00
xcu_dsp_map.v xilinx: Support multiplier mapping for all families. 2019-10-22 18:06:57 +02:00
xcup_urams.txt xilinx: Add URAM288 mapping for xcup 2019-10-23 11:47:44 +01:00
xcup_urams_map.v xilinx: Add URAM288 mapping for xcup 2019-10-23 11:47:44 +01:00