Clifford Wolf ed62fcdbe2 Fixed sign propagation in bit-wise operators		2013-07-09 23:53:55 +02:00
..
Makefile.inc	initial import	2013-01-05 11:13:26 +01:00
ast.cc	Fixed AST_CONSTANT node generation	2013-07-07 15:40:26 +02:00
ast.h	Major redesign of expr width/sign detecion (verilog/ast frontend)	2013-07-09 14:31:57 +02:00
genrtlil.cc	Fixed sign propagation in bit-wise operators	2013-07-09 23:53:55 +02:00
simplify.cc	Added defparam support to Verilog/AST frontend	2013-07-04 14:12:33 +02:00