Clifford Wolf 65f91e5120 Rename "write_verilog -nobasenradix" to "write_verilog -decimal"		2017-10-03 17:31:21 +02:00
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achronix	Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now	2017-10-01 11:04:17 -05:00
common	Add dff2ff.v techmap file	2017-05-31 11:45:58 +02:00
coolrunner2	coolrunner2: Finish fixing special-use p-terms	2017-09-01 07:22:16 -07:00
easic	Add first draft of eASIC back-end	2017-09-29 17:53:43 +02:00
gowin	Indenting fixes in gowin sim cell lib	2016-11-08 18:54:00 +01:00
greenpak4	Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted.	2017-09-14 10:26:32 -07:00
ice40	Fix synth_ice40 doc regarding -top default	2017-09-29 17:52:57 +02:00
intel	Rename "write_verilog -nobasenradix" to "write_verilog -decimal"	2017-10-03 17:31:21 +02:00
xilinx	Add techlibs/xilinx/lut2lut.v	2017-07-10 12:09:05 +02:00
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00