mirror of https://github.com/YosysHQ/yosys.git
There will soon be more (versioned) memory cells, so handle passes that only care if a cell is memory-related by a simple helper call instead of a hardcoded list. |
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.. | ||
aiger | ||
blif | ||
btor | ||
cxxrtl | ||
edif | ||
firrtl | ||
intersynth | ||
json | ||
protobuf | ||
rtlil | ||
simplec | ||
smt2 | ||
smv | ||
spice | ||
table | ||
verilog |