mirror of https://github.com/YosysHQ/yosys.git
Removing some signed checks and logic where we've already guaranteed the values to be positive. Indeed, in these cases, if a negative value got through (per my realisation in the signed fuzz harness), it would cause an infinite loop due to flooring division. |
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aiger | ||
blif | ||
btor | ||
cxxrtl | ||
edif | ||
firrtl | ||
intersynth | ||
jny | ||
json | ||
rtlil | ||
simplec | ||
smt2 | ||
smv | ||
spice | ||
table | ||
verilog |