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yosys/frontends/verilog
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Clifford Wolf 5308c1e02a Fixed bug in verilog parser 2015-10-15 15:19:23 +02:00
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.gitignore Updated .gitignore file for ilang and verilog frontends 2014-10-15 01:14:38 +02:00
Makefile.inc Adjust makefiles to work with out-of-tree builds 2015-08-12 15:04:44 +02:00
const2ast.cc Fixed segfault on invalid verilog constant 1'b_ 2015-09-22 08:13:09 +02:00
preproc.cc SystemVerilog also has assume(), added implicit -D FORMAL 2015-10-13 14:21:20 +02:00
verilog_frontend.cc SystemVerilog also has assume(), added implicit -D FORMAL 2015-10-13 14:21:20 +02:00
verilog_frontend.h Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
verilog_lexer.l SystemVerilog also has assume(), added implicit -D FORMAL 2015-10-13 14:21:20 +02:00
verilog_parser.y Fixed bug in verilog parser 2015-10-15 15:19:23 +02:00