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.gitignore
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added more .gitignore files (make test)
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2013-01-05 11:35:52 +01:00 |
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aes_kexp128.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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always01.v
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Added test cases from 2012 paper on comparison of foss verilog synthesis tools
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2013-03-31 11:17:56 +02:00 |
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always02.v
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Added test cases from 2012 paper on comparison of foss verilog synthesis tools
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2013-03-31 11:17:56 +02:00 |
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always03.v
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Added test cases from 2012 paper on comparison of foss verilog synthesis tools
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2013-03-31 11:17:56 +02:00 |
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arrays01.v
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Added test cases from 2012 paper on comparison of foss verilog synthesis tools
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2013-03-31 11:17:56 +02:00 |
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constpower.v
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Fixed handling of power operator
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2013-11-07 22:20:00 +01:00 |
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dff_different_styles.v
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Added support for complex set-reset flip-flops in proc_dff
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2013-10-24 16:54:05 +02:00 |
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fiedler-cooley.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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forgen01.v
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Added test cases from 2012 paper on comparison of foss verilog synthesis tools
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2013-03-31 11:17:56 +02:00 |
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forgen02.v
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Added test cases from 2012 paper on comparison of foss verilog synthesis tools
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2013-03-31 11:17:56 +02:00 |
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fsm.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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generate.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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i2c_master_tests.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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loops.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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mem2reg.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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mem_arst.v
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Renamed hansimem.v test case to mem_arst.v
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2013-03-24 15:25:08 +01:00 |
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memory.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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muxtree.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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omsp_dbg_uart.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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operators.v
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Added support for "2**n" shifter encoding
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2013-08-12 14:47:50 +02:00 |
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paramods.v
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Added defparam support to Verilog/AST frontend
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2013-07-04 14:12:33 +02:00 |
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process.v
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Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values
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2013-04-13 21:19:10 +02:00 |
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run-test.sh
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added ckeck for Icarus Verilog, otherwise the tests are silently stopped
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2013-03-17 09:05:15 +01:00 |
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signedexpr.v
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Major redesign of expr width/sign detecion (verilog/ast frontend)
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2013-07-09 14:31:57 +02:00 |
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subbytes.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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task_func.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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usb_phy_tetsts.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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values.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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vloghammer.v
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Behavior should be identical now to rev. 0b4a64ac6a (next: testing before constfold fixes)
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2013-11-02 21:13:01 +01:00 |
fc6dc0d7b8