Eddie Hung 988e6163ab Add _nowide variants of LUT libraries in -nowidelut flows		2019-06-26 10:23:29 -07:00
..
tests	Improved xilinx "bram1" test	2015-04-09 17:12:12 +02:00
.gitignore	Added support for initialized xilinx brams	2015-04-06 17:07:10 +02:00
Makefile.inc	Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}	2019-06-14 10:51:11 -07:00
abc_xc7.box	Realistic delays for RAM32X1D too	2019-06-25 09:34:28 -07:00
abc_xc7.lut	Simplify comment	2019-06-17 19:14:41 -07:00
abc_xc7_nowide.lut	Add _nowide variants of LUT libraries in -nowidelut flows	2019-06-26 10:23:29 -07:00
arith_map.v	Instead of MUXCY/XORCY use CARRY4 (with timing)	2019-05-21 16:19:45 -07:00
brams.txt	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
brams_bb.v	Remove WIP ABC9 flop support	2019-06-14 10:37:52 -07:00
brams_init.py	Squelch trailing whitespace, including meta-whitespace	2018-03-11 16:03:41 +01:00
brams_map.v	Revert BRAM WRITE_MODE changes.	2019-03-04 09:22:22 -08:00
cells_map.v	Fix name clash	2019-06-13 14:27:07 -07:00
cells_sim.v	Add RAM32X1D box info	2019-06-25 09:34:19 -07:00
cells_xtra.sh	Merge remote-tracking branch 'origin/master' into xaig	2019-06-25 09:33:11 -07:00
cells_xtra.v	Merge remote-tracking branch 'origin/master' into xaig	2019-06-25 09:33:11 -07:00
drams.txt	Add RAM32X1D support	2019-06-24 16:16:50 -07:00
drams_map.v	Add RAM32X1D support	2019-06-24 16:16:50 -07:00
ff_map.v	Cleanup	2019-06-05 12:28:46 -07:00
lut_map.v	Really permute Xilinx LUT mappings as default LUT6.I5:A6	2019-06-18 11:48:48 -07:00
synth_xilinx.cc	Add _nowide variants of LUT libraries in -nowidelut flows	2019-06-26 10:23:29 -07:00