mirror of https://github.com/YosysHQ/yosys.git
53 lines
1.6 KiB
Plaintext
53 lines
1.6 KiB
Plaintext
# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
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# NB: Inputs/Outputs must be ordered alphabetically
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# (with exceptions for carry in/out)
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# F7BMUX slower than F7AMUX
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# Inputs: I0 I1 S0
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# Outputs: O
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F7BMUX 1 1 3 1
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217 223 296
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# Inputs: I0 I1 S0
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# Outputs: O
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MUXF8 2 1 3 1
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104 94 273
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# CARRY4 + CARRY4_[ABCD]X
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# Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
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# Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3
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# (NB: carry chain input/output must be last
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# input/output and have been moved there
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# overriding the alphabetical ordering)
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CARRY4 3 1 10 8
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482 - - - - 223 - - - 222
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598 407 - - - 400 205 - - 334
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584 556 537 - - 523 558 226 - 239
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642 615 596 438 - 582 618 330 227 313
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536 379 - - - 340 - - - 271
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494 465 445 - - 433 469 - - 157
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592 540 520 356 - 512 548 292 - 228
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580 526 507 398 385 508 528 378 380 114
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# SLICEM/A6LUT
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# Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE
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# Outputs: DPO SPO
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RAM32X1D 4 0 13 2
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- - - - - - 631 472 407 238 127 - -
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631 472 407 238 127 - - - - - - - -
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# SLICEM/A6LUT
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# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
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# Outputs: DPO SPO
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RAM64X1D 5 0 15 2
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- - - - - - - 642 631 472 407 238 127 - -
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642 631 472 407 238 127 - - - - - - - - -
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# SLICEM/A6LUT + F7[AB]MUX
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# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
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# Outputs: DPO SPO
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RAM128X1D 6 0 17 2
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- - - - - - - - 1009 998 839 774 605 494 450 - -
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1047 1036 877 812 643 532 478 - - - - - - - - - -
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