mirror of https://github.com/YosysHQ/yosys.git
a2f9ebe43a
This maps memories for a global clock based formal verification flow. This implies -keepdc, uses $ff cells for ROMs and sets hdlname attributes. |
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.. | ||
cmds | ||
equiv | ||
fsm | ||
hierarchy | ||
memory | ||
opt | ||
pmgen | ||
proc | ||
sat | ||
techmap | ||
tests |