Clifford Wolf 6991c132b5 Add Xilinx RAM64X1D and RAM128X1D simulation models		2018-03-07 17:31:48 +01:00
..
achronix	Organizing Speedster file names	2017-11-08 20:23:55 -06:00
common	Add "synth -noshare"	2018-03-04 17:13:45 +01:00
coolrunner2	coolrunner2: Move LOC attributes onto the IO cells	2018-01-17 16:17:32 -08:00
easic	Add first draft of eASIC back-end	2017-09-29 17:53:43 +02:00
gowin	Indenting fixes in gowin sim cell lib	2016-11-08 18:54:00 +01:00
greenpak4	Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted.	2017-09-14 10:26:32 -07:00
ice40	Fix port names in SB_IO_OD	2017-12-10 15:33:38 +00:00
intel	Add "dffinit -highlow" and fix synth_intel	2018-01-09 18:42:19 +01:00
xilinx	Add Xilinx RAM64X1D and RAM128X1D simulation models	2018-03-07 17:31:48 +01:00
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00