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yosys/techlibs/ice40
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Tim 'mithro' Ansell d6bdefd2e9 Improving vpr output support. 
* Support output BLIF for Xilinx architectures.
 * Support using .names in BLIF for Xilinx architectures.
 * Use the same `NO_LUT` define in both `synth_ice40` and
  `synth_xilinx`.
 		2018-04-18 16:55:12 -07:00
..
tests Initialization support for all iCE40 bram modes 2015-04-26 08:39:31 +02:00
.gitignore Initialization support for all iCE40 bram modes 2015-04-26 08:39:31 +02:00
Makefile.inc Added synth_ice40 support for latches via logic loops 2016-05-06 23:02:37 +02:00
arith_map.v Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
brams.txt Added read-enable to memory model 2015-09-25 12:23:11 +02:00
brams_init.py Switched to Python 3 2015-08-22 09:59:33 +02:00
brams_map.v Fixed WE/RE usage in iCE40 BRAM mapping 2015-11-24 10:51:34 +01:00
cells_map.v Improving vpr output support. 2018-04-18 16:55:12 -07:00
cells_sim.v Squelch trailing whitespace, including meta-whitespace 2018-03-11 16:03:41 +01:00
ice40_ffinit.cc Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations 2016-07-08 14:41:36 +02:00
ice40_ffssr.cc Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations 2016-07-08 14:41:36 +02:00
ice40_opt.cc Fixed ice40_opt lut unmapping, added "ice40_opt -unlut" 2016-05-06 14:32:32 +02:00
latches_map.v Added synth_ice40 support for latches via logic loops 2016-05-06 23:02:37 +02:00
synth_ice40.cc Improving vpr output support. 2018-04-18 16:55:12 -07:00