Clifford Wolf 584d2030bf Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>		2019-03-29 16:32:44 +01:00
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.gitignore	Add "make coverage"	2018-08-27 14:22:21 +02:00
Makefile.inc	Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906	2019-03-29 16:32:44 +01:00
const2ast.cc	Convert more log_error() to log_file_error() where possible.	2018-07-20 09:37:44 -07:00
preproc.cc	Support SystemVerilog `` extension for macros	2018-05-17 00:09:56 -04:00
verilog_frontend.cc	Improve read_verilog debug output capabilities	2019-03-21 20:52:29 +01:00
verilog_frontend.h	Add "read_verilog -noassert -noassume -assert-assumes"	2018-09-24 20:51:16 +02:00
verilog_lexer.l	Fix handling of cases that look like sva labels, fixes #862	2019-03-10 16:27:18 -07:00
verilog_parser.y	Fix handling of cases that look like sva labels, fixes #862	2019-03-10 16:27:18 -07:00