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7319951145
yosys
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techlibs
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Clifford Wolf
7319951145
Added memory_bram "make_outreg" feature
2015-04-09 16:08:54 +02:00
..
cmos
Fixes in cmos_cells.v
2015-03-25 09:00:41 +01:00
common
make all vector-size related integer params in $mem sim model signed
2015-04-05 17:26:53 +02:00
ice40
Added very first version of "synth_ice40"
2015-03-05 20:37:55 +01:00
xilinx
Added memory_bram "make_outreg" feature
2015-04-09 16:08:54 +02:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00