yosys/passes
Clifford Wolf 6ff46323a3 Improved write address decoder generation memory_map 2014-08-30 18:18:15 +02:00
..
abc Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ 2014-08-16 18:29:39 +02:00
cmds Implemented "rename -enumerate -pattern" 2014-08-26 12:51:08 +02:00
fsm Don't change existing binary FSM encoding if it is already optimal 2014-08-30 14:43:06 +02:00
hierarchy Added module->ports 2014-08-14 16:22:52 +02:00
memory Improved write address decoder generation memory_map 2014-08-30 18:18:15 +02:00
opt Optimize shift ops with constant rhs in opt_const 2014-08-24 17:08:43 +02:00
proc Fixed handling of constant-true branches in proc_clean 2014-08-12 17:35:22 +02:00
sat azonenberg: Make dump_vcd save model when temporal induction fails due to step limit 2014-08-24 13:27:40 +02:00
techmap Fixed inserting of Q-inverters in dfflibmap 2014-08-27 19:44:12 +02:00
tests Changed backend-api from FILE to std::ostream 2014-08-23 13:54:21 +02:00