yosys/techlibs
Miodrag Milanovic 6e4c1675e7 Generate TRELLIS_DPR16X4 for lutram 2023-04-06 09:10:14 +02:00
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achronix Test fixes for latest iverilog 2022-09-21 15:46:43 +02:00
anlogic anlogic: Use `memory_libmap` pass. 2022-05-18 17:32:56 +02:00
common Add bitwise `$bweqx` and `$bwmux` cells 2022-11-30 18:24:35 +01:00
coolrunner2 Blackbox all whiteboxes after synthesis 2021-03-17 21:07:20 +00:00
easic Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
ecp5 Add additional iopad_external_pin attributes 2023-03-20 09:17:22 +01:00
efinix efinix: Use `memory_libmap` pass. 2022-05-18 17:32:56 +02:00
fabulous fabulous: Add support for mapping carry chains 2023-02-27 09:50:34 +01:00
gatemate gatemate: Enable register initialization 2023-02-15 17:29:01 +01:00
gowin Merge pull request #3663 from uis246/master 2023-02-28 06:56:01 +01:00
greenpak4 Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
ice40 ice40: Fix path delay definitions 2023-03-10 10:48:05 +01:00
intel Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
intel_alm Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
machxo2 Generate TRELLIS_DPR16X4 for lutram 2023-04-06 09:10:14 +02:00
nexus nexus: Fix BRAM write enable in PDP mode 2023-01-04 17:59:36 +01:00
quicklogic Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
sf2 Test fixes for latest iverilog 2022-09-21 15:46:43 +02:00
xilinx Update Xilinx cell definitions, fixes #3699 2023-03-23 09:44:36 +01:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00