mirror of https://github.com/YosysHQ/yosys.git
fabulous: Add support for mapping carry chains
Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat
myrtle
parent
8216b23fb7
commit
2ab3747cc9
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@ -8,3 +8,4 @@ $(eval $(call add_share_file,share/fabulous,techlibs/fabulous/ff_map.v))
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$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/ram_regfile.txt))
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$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/regfile_map.v))
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$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/io_map.v))
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$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/arith_map.v))
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@ -0,0 +1,65 @@
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`default_nettype none
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`ifdef ARITH_ha
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(* techmap_celltype = "$alu" *)
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module _80_fabulous_ha_alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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parameter _TECHMAP_CONSTMSK_CI_ = 0;
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parameter _TECHMAP_CONSTVAL_CI_ = 0;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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input CI, BI;
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(* force_downto *)
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output [Y_WIDTH-1:0] X, Y, CO;
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(* force_downto *)
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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(* force_downto *)
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wire [Y_WIDTH-1:0] AA = A_buf;
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(* force_downto *)
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wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
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wire [Y_WIDTH:0] CARRY;
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LUT4_HA #(
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.INIT(16'b0),
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.I0MUX(1'b1)
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) carry_statrt (
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.I0(), .I1(CI), .I2(CI), .I3(),
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.Ci(),
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.Co(CARRY[0])
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);
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// Carry chain
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genvar i;
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generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
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LUT4_HA #(
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.INIT(16'b1001_0110_1001_0110), // full adder sum over (I2, I1, I0)
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.I0MUX(1'b1)
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) lut_i (
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.I0(), .I1(AA[i]), .I2(BB[i]), .I3(),
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.Ci(CARRY[i]),
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.O(Y[i]),
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.Co(CARRY[i+1])
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);
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assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));
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end endgenerate
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assign X = AA ^ BB;
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endmodule
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`endif
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@ -24,6 +24,20 @@ module LUT4(output O, input I0, I1, I2, I3);
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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module LUT4_HA(output O, Co, input I0, I1, I2, I3, Ci);
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parameter [15:0] INIT = 0;
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parameter I0MUX = 1'b1;
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wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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wire I0_sel = I0MUX ? Ci : I0;
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assign O = I0_sel ? s1[1] : s1[0];
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assign Co = (Ci & I1) | (Ci & I2) | (I1 & I2);
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endmodule
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module LUTFF(input CLK, D, output reg O);
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initial O = 1'b0;
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always @ (posedge CLK) begin
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@ -83,6 +83,9 @@ struct SynthPass : public ScriptPass
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log(" do not run 'alumacc' pass. i.e. keep arithmetic operators in\n");
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log(" their direct form ($add, $sub, etc.).\n");
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log("\n");
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log(" -carry <none|ha>\n");
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log(" carry mapping style (none, half-adders, ...) default=none\n");
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log("\n");
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log(" -noregfile\n");
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log(" do not map register files\n");
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log("\n");
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@ -119,7 +122,7 @@ struct SynthPass : public ScriptPass
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log("\n");
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}
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string top_module, json_file, blif_file, plib, fsm_opts, memory_opts;
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string top_module, json_file, blif_file, plib, fsm_opts, memory_opts, carry_mode;
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std::vector<string> extra_plib, extra_map;
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bool autotop, forvpr, noalumacc, nofsm, noshare, noregfile, iopad, complexdff, flatten;
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@ -137,6 +140,7 @@ struct SynthPass : public ScriptPass
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noshare = false;
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iopad = false;
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complexdff = false;
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carry_mode = "none";
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flatten = true;
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json_file = "";
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blif_file = "";
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@ -229,6 +233,12 @@ struct SynthPass : public ScriptPass
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complexdff = true;
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continue;
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}
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if (args[argidx] == "-carry") {
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carry_mode = args[++argidx];
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if (carry_mode != "none" && carry_mode != "ha")
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log_cmd_error("Unsupported carry style: %s\n", carry_mode.c_str());
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continue;
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}
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if (args[argidx] == "-noflatten") {
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flatten = false;
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continue;
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@ -326,7 +336,8 @@ struct SynthPass : public ScriptPass
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if (check_label("map_gates")) {
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run("opt -full");
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run("techmap -map +/techmap.v");
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run(stringf("techmap -map +/techmap.v -map +/fabulous/arith_map.v -D ARITH_%s",
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help_mode ? "<carry>" : carry_mode.c_str()));
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run("opt -fast");
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}
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@ -0,0 +1,9 @@
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read_verilog ../common/add_sub.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/fabulous/prims.v synth_fabulous -carry ha # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-max 10 t:LUT4_HA
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select -assert-max 4 t:LUT1
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select -assert-none t:LUT1 t:LUT4_HA %% t:* %D
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