yosys/passes/techmap
Clifford Wolf 03c96f9ce7 Added "techmap -map %{design-name}" 2014-07-29 16:35:13 +02:00
..
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00
Makefile.inc Added "make SMALL=1" 2014-07-24 19:03:57 +02:00
dfflibmap.cc Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
extract.cc Added "techmap -map %{design-name}" 2014-07-29 16:35:13 +02:00
filterlib.cc Moved dfflibmap from passes/dfflibmap to passes/techmap 2013-10-16 15:32:26 +02:00
hilomap.cc Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
iopadmap.cc Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
libparse.cc Fixed dumping of timing() { .. } block in libparse 2014-03-09 15:16:07 +01:00
libparse.h renamed LibertyParer to LibertyParser 2014-01-14 18:57:47 +01:00
simplemap.cc Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
techmap.cc Added "techmap -map %{design-name}" 2014-07-29 16:35:13 +02:00