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aiger
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tests/aiger: Add missing .gitignore
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2020-02-15 19:52:21 +01:00 |
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arch
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fix argument order for macOS compatibility
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2020-03-18 15:11:49 +01:00 |
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asicworld
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Fix FIRRTL to Verilog process instance subfield assignment.
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2019-02-25 16:18:13 -08:00 |
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bram
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Added support for (single-clock) transparent memories to bram tests
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2016-11-01 10:03:13 +01:00 |
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errors
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Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
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2018-10-25 02:37:56 +03:00 |
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fsm
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Speed up "make test" and related cleanups
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2019-08-17 14:37:07 +02:00 |
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hana
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Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
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2016-09-22 11:49:29 -06:00 |
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liberty
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Liberty file parser now accepts superfluous ;
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2019-03-27 15:16:19 +01:00 |
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lut
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Forgot to commit
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2019-07-16 12:44:26 -07:00 |
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memfile
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Added 'set -e' into tests/memfile/run-test.sh
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2020-02-06 10:45:40 -03:00 |
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memories
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memory_dff: Fix checking of feedback mux input when more than one mux
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2019-07-02 13:35:50 +01:00 |
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opt
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Merge pull request #1576 from YosysHQ/eddie/opt_merge_init
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2020-02-05 14:56:26 -08:00 |
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opt_share
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Support various binary operators in opt_share
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2019-08-04 19:06:38 +02:00 |
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proc
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proc_clean: fix order of switch insertion.
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2019-08-19 16:44:23 +00:00 |
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realmath
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Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
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2016-09-22 11:49:29 -06:00 |
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rpc
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rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors
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2020-03-06 15:29:01 +01:00 |
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sat
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Merge pull request #1638 from YosysHQ/eddie/fix1631
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2020-02-05 19:31:18 +01:00 |
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select
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Do not warn on empty selection with prefixed `arg_memb`.
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2020-03-23 17:50:11 +00:00 |
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share
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Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
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2016-09-22 11:49:29 -06:00 |
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simple
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Fix partsel expr bit width handling and add test case
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2020-03-08 16:12:12 +01:00 |
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simple_abc9
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Update simple_abc9 tests
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2020-02-27 10:17:29 -08:00 |
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smv
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Progress in SMV back-end
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2015-06-19 14:08:46 +02:00 |
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sva
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Fix "verific -extnets" for more complex situations
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2019-03-26 14:17:46 +01:00 |
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svinterfaces
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Fix typo in tests/svinterfaces/runone.sh
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2019-05-03 14:40:51 +02:00 |
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svtypes
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Support module/package/interface/block scope for typedef names.
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2020-03-23 20:07:22 +00:00 |
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techmap
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techmap: Fix cell names with _TECHMAP_REPLACE_.*
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2020-03-23 11:17:07 +01:00 |
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tools
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autotest.sh to define _AUTOTB when test_autotb
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2019-06-28 14:56:22 -07:00 |
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unit
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Build hotfix in tests/unit/Makefile
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2016-12-11 10:58:49 +01:00 |
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various
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Add support for SystemVerilog-style `define to Verilog frontend
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2020-03-27 16:08:26 +00:00 |
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vloghtb
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bugfix in blif front-end
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2015-05-18 11:15:49 +02:00 |
d5e2061687