whitequark 9ef078848a gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.		2018-12-05 17:13:27 +00:00
..
.gitignore	Added first help messages for cell types	2015-10-14 16:27:42 +02:00
Makefile.inc	gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.	2018-12-05 17:13:27 +00:00
adff2dff.v	Added adff2dff.v (for techmap -share_map)	2014-08-07 16:14:38 +02:00
cellhelp.py	Progress on cell help messages	2015-10-17 02:35:19 +02:00
cells.lib	Added cells.lib	2015-01-16 15:50:42 +01:00
dff2ff.v	Add dff2ff.v techmap file	2017-05-31 11:45:58 +02:00
gate2lut.v	gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.	2018-12-05 17:13:27 +00:00
pmux2mux.v	Added techlibs/common/pmux2mux.v	2014-01-17 20:06:15 +01:00
prep.cc	Consistent use of 'override' for virtual methods in derived classes.	2018-07-20 23:51:06 -07:00
simcells.v	Fix typo.	2018-12-05 17:13:27 +00:00
simlib.v	Add $allconst and $allseq cell types	2018-02-23 13:14:47 +01:00
synth.cc	Consistent use of 'override' for virtual methods in derived classes.	2018-07-20 23:51:06 -07:00
techmap.v	Added $ff and $_FF_ cell types	2016-10-12 01:18:39 +02:00