Icenowy Zheng 634d7d1c14 Revert "Leave only real black box cells" ... This reverts commit 43030db5ff. For a synthesis tool, generating EG_LOGIC cells are a good choice, as they can be furtherly optimized when PnR, although sometimes EG_LOGIC is not as blackbox as EG_PHY cells (because the latter is more close to the hardware implementation). Signed-off-by: Icenowy Zheng <icenowy@aosc.io>		2018-12-17 23:20:40 +08:00
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achronix	Consistent use of 'override' for virtual methods in derived classes.	2018-07-20 23:51:06 -07:00
anlogic	Revert "Leave only real black box cells"	2018-12-17 23:20:40 +08:00
common	gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.	2018-12-05 17:13:27 +00:00
coolrunner2	Consistent use of 'override' for virtual methods in derived classes.	2018-07-20 23:51:06 -07:00
easic	Consistent use of 'override' for virtual methods in derived classes.	2018-07-20 23:51:06 -07:00
ecp5	ecp5: Add 'fake' DCU parameters	2018-11-09 18:25:42 +00:00
gowin	Changes in GoWin synth commands and ALU primitive support	2018-12-03 20:08:35 -06:00
greenpak4	Consistent use of 'override' for virtual methods in derived classes.	2018-07-20 23:51:06 -07:00
ice40	Rename "fine:" label to "map:" in "synth_ice40"	2018-12-16 16:36:19 +01:00
intel	Changes in GoWin synth commands and ALU primitive support	2018-12-03 20:08:35 -06:00
sf2	Fix sf2 LUT interface	2018-10-31 15:36:53 +01:00
xilinx	Add support for Xilinx PS7 block	2018-11-10 12:45:07 -08:00
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00