yosys/frontends
Clifford Wolf 012c6af088 Allow $specify[23] cells in blackbox modules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
..
aiger Add log_debug() framework 2019-04-22 17:25:52 +02:00
ast Allow $specify[23] cells in blackbox modules 2019-04-23 21:36:59 +02:00
blif Add missing "[options]" to read_blif help 2019-02-08 12:41:39 -08:00
ilang Add "read_ilang -lib" 2019-04-05 17:31:49 +02:00
json Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
liberty Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00
verific Add "read -verific" and "read -noverific" 2019-03-27 14:03:35 +01:00
verilog Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature 2019-04-23 21:36:59 +02:00