yosys/passes
Eddie Hung 5c8344363f Revert "Trim shiftx_width when upper bits are 1'bx"
This reverts commit 7e7965ca7b.
2019-08-21 19:18:27 -07:00
..
cmds More use of IdString::in() 2019-08-15 09:23:57 -07:00
equiv substr() -> compare() 2019-08-07 12:20:08 -07:00
fsm RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
hierarchy stoi -> atoi 2019-08-07 11:09:17 -07:00
memory stoi -> atoi 2019-08-07 11:09:17 -07:00
opt opt_expr to trim A port of $shiftx if Y_WIDTH == 1 2019-08-21 19:18:05 -07:00
pmgen Revert "Trim shiftx_width when upper bits are 1'bx" 2019-08-21 19:18:27 -07:00
proc proc_clean: fix order of switch insertion. 2019-08-19 16:44:23 +00:00
sat More use of IdString::in() 2019-08-15 09:23:57 -07:00
techmap Grammar 2019-08-20 20:05:51 -07:00
tests More use of IdString::in() 2019-08-15 09:23:57 -07:00