yosys/passes
Jannis Harder bbdfcfdf30 clk2fflogic: Fix handling of $check cells
Fixes a bug in the handling of the recently introduced $check cells.
Both $check and $print cells in clk2fflogic are handled by the same code
and the existing tests for that were only using $print cells. This
missed a bug where the additional A signal of $check cells that is not
present on $print cells was dropped due to a typo, rendering $check
cells non-functional.

Also updates the tests to explicitly cover both cell types such that
they would have detected the now fixed bug.
2024-02-14 11:42:27 +01:00
..
cmds Merge pull request #4174 from YosysHQ/claire/overwrite 2024-02-05 23:49:24 +01:00
equiv equiv_simple: Fix seed handling in non-short mode 2023-10-03 13:05:42 +02:00
fsm add option to fsm_detect to ignore self-resetting 2023-01-30 16:12:53 +01:00
hierarchy hierarchy: Without a known top module, derive all deferred modules 2024-02-06 10:31:40 +01:00
memory Fix printf formats 2024-01-15 12:07:54 +01:00
opt Merge pull request #4084 from jix/scopeinfo 2024-02-12 09:51:22 +01:00
pmgen Address `SigBit`/`SigSpec` confusion issues under c++20 2024-02-08 17:48:36 +01:00
proc proc_clean: only consider fully-defined switch operands too. 2023-08-12 02:46:31 +02:00
sat clk2fflogic: Fix handling of $check cells 2024-02-14 11:42:27 +01:00
techmap Merge pull request #4084 from jix/scopeinfo 2024-02-12 09:51:22 +01:00
tests Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00