riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/passes
History
Marcelina Kościelnicka 54e75129e5 opt_lut: Allow more than one -dlogic per cell type. 
Fixes #2061.
 		2021-07-29 17:30:07 +02:00
..
cmds rtlil: Make Process handling more uniform with Cell and Wire. 2021-07-12 00:47:34 +02:00
equiv Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
fsm Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
hierarchy Use new read_id_num helper function elsewhere in hierarchy.cc 2021-07-20 10:13:15 -04:00
memory Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
opt opt_lut: Allow more than one -dlogic per cell type. 2021-07-29 17:30:07 +02:00
pmgen Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
proc proc: Run opt_expr at the end 2021-07-27 20:44:45 +02:00
sat memory: Introduce $meminit_v2 cell, with EN input. 2021-07-28 23:18:38 +02:00
techmap Fix deadname SVN links 2021-06-09 12:44:37 +02:00
tests Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00