Robert Ou 4af5baab21 coolrunner2: Initial mapping of DFFs ... All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N (negative-edge triggered)		2017-06-25 23:58:28 -07:00
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altera_intel	Squelch trailing whitespace	2017-04-12 15:11:09 +02:00
common	Add dff2ff.v techmap file	2017-05-31 11:45:58 +02:00
coolrunner2	coolrunner2: Initial mapping of DFFs	2017-06-25 23:58:28 -07:00
gowin	Indenting fixes in gowin sim cell lib	2016-11-08 18:54:00 +01:00
greenpak4	greenpak4_counters: Added support for parallel output from GP_COUNTx cells	2017-05-22 19:39:55 -07:00
ice40	iCE40 flow is not experimental anymore	2016-11-01 11:32:02 +01:00
xilinx	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00