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yosys/passes/opt
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Clifford Wolf 1f1deda888 Added non-std verilog assume() statement 2015-02-26 18:47:39 +01:00
..
Makefile.inc Fixed build with SMALL=1 2014-12-30 11:41:24 +01:00
opt.cc Some cleanups in "clean" 2015-02-24 22:31:30 +01:00
opt_clean.cc Added non-std verilog assume() statement 2015-02-26 18:47:39 +01:00
opt_const.cc Using design->selected_modules() in opt_* 2015-02-03 23:45:01 +01:00
opt_muxtree.cc Using design->selected_modules() in opt_* 2015-02-03 23:45:01 +01:00
opt_reduce.cc Using design->selected_modules() in opt_* 2015-02-03 23:45:01 +01:00
opt_rmdff.cc Don't be too smart with $dff cells with "init" attribute on out signal 2014-10-16 11:49:31 +02:00
opt_share.cc Using design->selected_modules() in opt_* 2015-02-03 23:45:01 +01:00
share.cc Replaced ezDefaultSAT with ezSatPtr 2015-02-21 12:15:41 +01:00
wreduce.cc wreduce help typo fix 2015-02-17 13:02:16 +01:00