Clifford Wolf 7daad40ca4 Fixed counting verilog line numbers for "// synopsys translate_off" sections		2014-07-30 20:18:48 +02:00
..
ast	Added $shift and $shiftx cell types (needed for correct part select behavior)	2014-07-29 16:35:13 +02:00
ilang	Added wire->upto flag for signals such as "wire [0:7] x;"	2014-07-28 12:12:13 +02:00
liberty	Refactoring: Renamed RTLIL::Design::modules to modules_	2014-07-27 11:18:30 +02:00
verific	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
verilog	Fixed counting verilog line numbers for "// synopsys translate_off" sections	2014-07-30 20:18:48 +02:00
vhdl2verilog	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00