yosys/frontends/verilog
Clifford Wolf 7daad40ca4 Fixed counting verilog line numbers for "// synopsys translate_off" sections 2014-07-30 20:18:48 +02:00
..
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00
Makefile.inc Added "make PRETTY=1" 2014-07-24 17:15:01 +02:00
const2ast.cc Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
lexer.l Fixed counting verilog line numbers for "// synopsys translate_off" sections 2014-07-30 20:18:48 +02:00
parser.y fixed parsing of constant with comment between size and value 2014-07-02 06:27:04 +02:00
preproc.cc Fixed counting verilog line numbers for "// synopsys translate_off" sections 2014-07-30 20:18:48 +02:00
verilog_frontend.cc Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
verilog_frontend.h Added read_verilog -sv options, added support for bit, logic, 2014-06-12 11:54:20 +02:00