yosys/backends
whitequark 41421f5dca ast, rpc: record original name of $paramod\* as \hdlname attribute.
The $paramod name mangling is not invertible (the \ character, which
separates the module name from the parameters, is valid in the module
name itself), which does not stop people from trying to invert it.

This commit makes it easy to invert the name mangling by storing
the original name explicitly, and fixes the firrtl backend to use
the newly introduced attribute.
2020-04-18 03:47:28 +00:00
..
aiger xaiger: add check for $__ABC9_DELAY model 2020-04-13 19:11:23 -07:00
blif kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
btor kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
cxxrtl cxxrtl: make ROMs writable, document memory::operator[]. 2020-04-16 16:45:54 +00:00
edif kernel: use more ID::* 2020-04-02 07:14:08 -07:00
firrtl ast, rpc: record original name of $paramod\* as \hdlname attribute. 2020-04-18 03:47:28 +00:00
ilang Clean up pseudo-private member usage in `backends/ilang/ilang_backend.cc`. 2020-04-01 03:08:39 +00:00
intersynth Clean up pseudo-private member usage in `backends/intersynth/intersynth.cc`. 2020-04-01 06:32:09 +00:00
json json: Update format documentation. 2020-04-15 16:12:14 +02:00
protobuf Add aiger and protobuf backends binary support 2019-09-28 09:51:48 +02:00
simplec kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
smt2 Merge pull request #1830 from boqwxp/qbfsat 2020-04-15 17:33:50 +02:00
smv kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
spice kernel: use more ID::* 2020-04-02 07:14:08 -07:00
table Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
verilog write_verilog: fix precondition check. 2020-04-14 12:12:50 +00:00