Clifford Wolf f71e27dbf1 Remove auto_wire framework (smarter than the verilog standard)		2013-11-24 17:29:11 +01:00
..
bitpattern.h	initial import	2013-01-05 11:13:26 +01:00
calc.cc	More undef-propagation related fixes	2013-11-08 11:40:36 +01:00
celltypes.h	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	2013-10-18 12:13:34 +02:00
consteval.h	Fixed handling of undef values in MUX select input in ConstEval	2013-11-06 17:33:20 +01:00
driver.cc	Some driver changes/fixes	2013-11-22 14:53:57 +01:00
log.cc	Added -v<level> option and some minor driver cleanups	2013-11-17 13:26:31 +01:00
log.h	Added more performance measurement infrastructure	2013-11-22 14:08:10 +01:00
register.cc	Call internal checker more often	2013-11-10 23:24:21 +01:00
register.h	Write yosys version to output files	2013-11-03 21:41:39 +01:00
rtlil.cc	Remove auto_wire framework (smarter than the verilog standard)	2013-11-24 17:29:11 +01:00
rtlil.h	Remove auto_wire framework (smarter than the verilog standard)	2013-11-24 17:29:11 +01:00
satgen.h	Added verification of SAT model to "eval -vloghammer_report" command	2013-11-09 11:38:17 +01:00
sigtools.h	Some fixes to improve determinism	2013-08-09 12:42:32 +02:00