This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
3dd3ab98c2
yosys
/
frontends
History
Eddie Hung
03ec8d6551
Run "clean" on mapped_mod in its own design
2019-08-07 09:54:27 -07:00
..
aiger
Run "clean" on mapped_mod in its own design
2019-08-07 09:54:27 -07:00
ast
Fix handling of functions/tasks without top-level begin-end block,
fixes
#1231
2019-08-06 18:06:14 +02:00
blif
Add missing "[options]" to read_blif help
2019-02-08 12:41:39 -08:00
ilang
Allow attributes on individual switch cases in RTLIL.
2019-07-08 11:34:58 +00:00
json
Update JSON front-end to process new attr/param encoding
2019-08-01 12:48:22 +02:00
liberty
Fix typo, double "of"
2019-07-16 11:03:30 +02:00
verific
Call "read_verilog" with -defer from "read"
2019-07-29 10:29:36 +02:00
verilog
verilog_lexer: Increase YY_BUF_SIZE to 65536
2019-07-26 13:35:39 +01:00