yosys/frontends/ast
Clifford Wolf f1f5b4e375 Fix handling of functions/tasks without top-level begin-end block, fixes #1231
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 18:06:14 +02:00
..
Makefile.inc Added Verilog/AST support for DPI functions (dpi_call() still unimplemented) 2014-08-21 12:43:51 +02:00
ast.cc initialize noblackbox and nowb in AstModule::clone 2019-07-22 10:37:40 +02:00
ast.h Add "read_verilog -pwires" feature, closes #1106 2019-06-19 14:38:50 +02:00
dpicall.cc Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
genrtlil.cc genrtlil: emit \src attribute on CaseRule. 2019-07-08 12:29:08 +00:00
simplify.cc Fix handling of functions/tasks without top-level begin-end block, fixes #1231 2019-08-06 18:06:14 +02:00