yosys/passes
Eddie Hung 592baebd22 xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only 2020-04-22 17:43:25 -07:00
..
cmds Merge pull request #1949 from YosysHQ/eddie/select_blackbox 2020-04-22 15:35:05 -07:00
equiv kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
fsm kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
hierarchy hierarchy: Convert positional parameters to named. 2020-04-21 19:09:00 +02:00
memory memory_bram: Fix ignorance of valid, matched rules 2020-04-10 21:48:04 +01:00
opt opt_expr: Fix X and CO outputs for $alu identity-mapping rules. 2020-04-16 11:48:29 +02:00
pmgen xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only 2020-04-22 17:43:25 -07:00
proc kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
sat sim: Fix handling of constant-connected cell inputs at startup 2020-04-21 08:58:52 +01:00
techmap abc9: -prep_lut to be more robust 2020-04-20 09:39:35 -07:00
tests Clean up `passes/tests/test_autotb.cc`. 2020-04-06 04:25:21 +00:00