yosys/passes
Clifford Wolf 3aa003c8e9 Using "NOT" instead of "INV" as cell name in default abc genlib file 2014-09-19 13:15:31 +02:00
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abc Using "NOT" instead of "INV" as cell name in default abc genlib file 2014-09-19 13:15:31 +02:00
cmds Alphabetically sort port names in "show" output 2014-09-19 11:13:10 +02:00
fsm Corrected spelling mistakes found by lintian 2014-09-06 08:47:06 +02:00
hierarchy Corrected spelling mistakes found by lintian 2014-09-06 08:47:06 +02:00
memory Fixed $memwr/$memrd order in memory_dff 2014-09-16 12:40:58 +02:00
opt Fixed wreduce $shiftx handling 2014-09-15 11:29:09 +02:00
proc Fixed handling of constant-true branches in proc_clean 2014-08-12 17:35:22 +02:00
sat Corrected spelling mistakes found by lintian 2014-09-06 08:47:06 +02:00
techmap More aggressive $macc merging in alumacc 2014-09-15 12:42:11 +02:00
tests Added $lcu cell type 2014-09-08 13:31:04 +02:00