mirror of https://github.com/YosysHQ/yosys.git
c77b7343d0
* Change simlib's $mux cell to use the ternary operator as $_MUX_ already does * Stop opt_expr -keepdc from changing S=x to S=0 * Change const eval of $mux and $pmux to match the updated simlib (fixes sim) * The sat behavior of $mux already matches the updated simlib The verilog frontend uses $mux for the ternary operators and this changes all interpreations of the $mux cell (that I found) to match the verilog simulation behavior for the ternary operator. For 'if' and 'case' expressions the frontend may also use $mux but uses $eqx if the verilog simulation behavior is requested with the '-ifx' option. For $pmux there is a remaining mismatch between the sat behavior and the simlib behavior. Resolving this requires more discussion, as the $pmux cell does not directly correspond to a specific verilog construct. |
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| .. | ||
| Makefile.inc | ||
| muxpack.cc | ||
| opt.cc | ||
| opt_clean.cc | ||
| opt_demorgan.cc | ||
| opt_dff.cc | ||
| opt_expr.cc | ||
| opt_ffinv.cc | ||
| opt_lut.cc | ||
| opt_lut_ins.cc | ||
| opt_mem.cc | ||
| opt_mem_feedback.cc | ||
| opt_mem_priority.cc | ||
| opt_mem_widen.cc | ||
| opt_merge.cc | ||
| opt_muxtree.cc | ||
| opt_reduce.cc | ||
| opt_share.cc | ||
| pmux2shiftx.cc | ||
| rmports.cc | ||
| share.cc | ||
| wreduce.cc | ||