yosys/techlibs
Alberto Gonzalez fc6b898178
Fix indentation in `techlibs/ice40/synth_ice40.cc`.
2020-04-01 16:29:56 +00:00
..
achronix Remove executable flag from files 2020-02-15 10:36:44 +01:00
anlogic synth_*: call 'opt -fast' after 'techmap' 2020-02-05 18:39:01 -08:00
common Fix invalid verilog syntax 2020-03-14 14:33:44 +01:00
coolrunner2 coolrunner2: Attempt to give wires/cells more meaningful names 2020-03-02 01:40:57 -08:00
easic Update doc that "-retime" calls abc with "-dff -D 1" 2019-12-30 13:28:29 -08:00
ecp5 Merge pull request #1716 from zeldin/ecp5_fix 2020-03-09 11:04:08 +01:00
efinix synth_*: call 'opt -fast' after 'techmap' 2020-02-05 18:39:01 -08:00
gowin Removing cells_sim.v from bram techmap pass 2020-02-06 14:38:29 -06:00
greenpak4 synth_*: call 'opt -fast' after 'techmap' 2020-02-05 18:39:01 -08:00
ice40 Fix indentation in `techlibs/ice40/synth_ice40.cc`. 2020-04-01 16:29:56 +00:00
intel Add log_experimental() and experimental() API and "yosys -x" 2020-01-27 18:27:47 +01:00
sf2 synth_*: call 'opt -fast' after 'techmap' 2020-02-05 18:39:01 -08:00
xilinx xilinx: Mark IOBUFDS.IOB as external pad 2020-03-20 14:37:38 +01:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00