whitequark 29d130dee9 ice40: remove impossible test. ... iCE40 does not have LUTRAM. This was erroneously added in commit caab66111e, and tested for BRAM, essentially a duplicate of the "dpram.ys" test.		2020-02-06 14:58:20 +00:00
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anlogic	Call equiv_opt with -multiclock and -assert	2019-12-31 18:39:32 -08:00
common	Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram	2019-12-16 21:48:21 -08:00
ecp5	Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux	2020-02-05 10:47:31 -08:00
efinix	Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux	2020-02-05 10:47:31 -08:00
gowin	Add opt_lut_ins pass. (#1673)	2020-02-03 14:57:17 +01:00
ice40	ice40: remove impossible test.	2020-02-06 14:58:20 +00:00
xilinx	abc9_ops: -reintegrate to use derived_type for box_ports	2020-02-05 14:46:48 -08:00
run-test.sh	Add simcells.v, simlib.v, and some output	2019-06-27 11:13:49 -07:00