Clifford Wolf a721f7d768 Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>		2014-07-18 11:36:34 +02:00
..
bitpattern.h	initial import	2013-01-05 11:13:26 +01:00
calc.cc	Strictly zero-extend unsigned A-inputs of shift operations	2014-03-06 11:53:37 +01:00
celltypes.h	Added support for dlatchsr cells	2014-03-31 14:14:40 +02:00
compatibility.cc	Merged OSX fixes from Siesh1oo with some modifications	2014-03-13 12:48:10 +01:00
compatibility.h	Hotfix for kernel/compatibility.h	2014-03-13 12:55:15 +01:00
consteval.h	Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux	2014-01-03 17:30:50 +01:00
driver.cc	Use "verilog -sv" to parse .sv files	2014-07-11 13:10:51 +02:00
log.cc	Merged OSX fixes from Siesh1oo with some modifications	2014-03-13 12:48:10 +01:00
log.h	Added log_id() helper function	2014-07-18 10:26:01 +02:00
register.cc	Improved error message for options after front-end filename arguments	2014-06-04 09:10:50 +02:00
register.h	- kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname().	2014-03-12 23:17:14 +01:00
rtlil.cc	Added function-like cell creation helpers	2014-07-18 10:27:06 +02:00
rtlil.h	Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>	2014-07-18 11:36:34 +02:00
satgen.h	Added libs/minisat (copy of minisat git master)	2014-03-12 10:17:51 +01:00
sigtools.h	Some fixes to improve determinism	2013-08-09 12:42:32 +02:00