mirror of https://github.com/YosysHQ/yosys.git
Strictly zero-extend unsigned A-inputs of shift operations
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@ -305,14 +305,14 @@ static RTLIL::Const const_shift(const RTLIL::Const &arg1, const RTLIL::Const &ar
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RTLIL::Const RTLIL::const_shl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool, int result_len)
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{
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RTLIL::Const arg1_ext = arg1;
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extend(arg1_ext, result_len, signed1);
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extend_u0(arg1_ext, result_len, signed1);
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return const_shift(arg1_ext, arg2, false, -1, result_len);
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}
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RTLIL::Const RTLIL::const_shr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool, int result_len)
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{
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RTLIL::Const arg1_ext = arg1;
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extend(arg1_ext, result_len, signed1);
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extend_u0(arg1_ext, result_len, signed1);
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return const_shift(arg1_ext, arg2, false, +1, result_len);
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}
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@ -634,7 +634,7 @@ struct SatGen
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while (undef_y.size() < undef_a.size())
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undef_y.push_back(ez->literal());
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while (undef_y.size() > undef_a.size())
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undef_a.push_back(undef_a.back());
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undef_a.push_back(cell->parameters["\\A_SIGNED"].as_bool() ? undef_a.back() : ez->FALSE);
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tmp = undef_a;
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for (size_t i = 0; i < b.size(); i++)
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