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.gitignore
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added more .gitignore files (make test)
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2013-01-05 11:35:52 +01:00 |
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aes_kexp128.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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always01.v
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Added test cases from 2012 paper on comparison of foss verilog synthesis tools
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2013-03-31 11:17:56 +02:00 |
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always02.v
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Added test cases from 2012 paper on comparison of foss verilog synthesis tools
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2013-03-31 11:17:56 +02:00 |
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always03.v
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Added test cases from 2012 paper on comparison of foss verilog synthesis tools
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2013-03-31 11:17:56 +02:00 |
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arraycells.v
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added tests for new verilog features
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2014-06-07 12:26:11 +02:00 |
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arrays01.v
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Added test cases from 2012 paper on comparison of foss verilog synthesis tools
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2013-03-31 11:17:56 +02:00 |
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carryadd.v
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Bugfix in name resolution with generate blocks
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2014-01-30 15:01:28 +01:00 |
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constpower.v
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Fixed handling of power operator
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2013-11-07 22:20:00 +01:00 |
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dff_different_styles.v
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Added support for complex set-reset flip-flops in proc_dff
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2013-10-24 16:54:05 +02:00 |
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fiedler-cooley.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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forgen01.v
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Progress in Verific bindings
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2014-03-17 01:56:00 +01:00 |
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forgen02.v
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Added test cases from 2012 paper on comparison of foss verilog synthesis tools
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2013-03-31 11:17:56 +02:00 |
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fsm.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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generate.v
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Various improvements in support for generate statements
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2013-12-04 21:06:54 +01:00 |
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hierarchy.v
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Implemented correct handling of signed module parameters
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2013-11-24 17:17:21 +01:00 |
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i2c_master_tests.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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loops.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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macros.v
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fixed parsing of constant with comment between size and value
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2014-07-02 06:27:04 +02:00 |
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mem2reg.v
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Added test case for AstNode::MEM2REG_FL_CMPLX_LHS
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2014-06-17 21:49:59 +02:00 |
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mem_arst.v
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Progress in Verific bindings
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2014-03-17 01:56:00 +01:00 |
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memory.v
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Implemented dynamic bit-/part-select for memory writes
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2014-07-17 16:49:23 +02:00 |
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multiplier.v
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Added multiplier test case from eda playground
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2013-12-18 13:43:53 +01:00 |
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muxtree.v
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Fixed parsing of default cases when not last case
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2013-11-18 16:10:50 +01:00 |
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omsp_dbg_uart.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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operators.v
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Added support for "2**n" shifter encoding
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2013-08-12 14:47:50 +02:00 |
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paramods.v
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Added defparam support to Verilog/AST frontend
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2013-07-04 14:12:33 +02:00 |
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partsel.v
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Implemented indexed part selects
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2013-11-20 13:05:27 +01:00 |
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process.v
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Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values
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2013-04-13 21:19:10 +02:00 |
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realexpr.v
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Fixed handling of mixed real/int ternary expressions
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2014-06-25 10:05:36 +02:00 |
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repwhile.v
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added tests for new verilog features
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2014-06-07 12:26:11 +02:00 |
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rotate.v
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Another name resolution bugfix for generate blocks
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2013-11-20 13:57:40 +01:00 |
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run-test.sh
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Added note to "make test": use git checkout of iverilog
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2014-07-16 10:03:07 +02:00 |
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signedexpr.v
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Major redesign of expr width/sign detecion (verilog/ast frontend)
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2013-07-09 14:31:57 +02:00 |
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sincos.v
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Fix in sincos testbench gen
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2013-12-04 09:24:52 +01:00 |
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subbytes.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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task_func.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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undef_eqx_nex.v
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Added proper === and !== support in constant expressions
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2013-12-27 13:50:08 +01:00 |
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usb_phy_tetsts.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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values.v
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Replaced RTLIL::Const::str with generic decoder method
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2013-12-04 14:14:05 +01:00 |
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vloghammer.v
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Behavior should be identical now to rev. 0b4a64ac6a (next: testing before constfold fixes)
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2013-11-02 21:13:01 +01:00 |
9b183539af