Clifford Wolf 251562a491 Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE ... Signed-off-by: Clifford Wolf <clifford@clifford.at>		2018-05-24 18:13:38 +02:00
..
ast	Replace -ignore_redef with -[no]overwrite	2018-05-03 15:25:59 +02:00
blif	Increase maximum LUT size in blifparse to 12 bits	2017-09-27 15:27:42 +02:00
ilang	Added avail params to ilang format, check module params in 'hierarchy -check'	2016-10-22 11:05:49 +02:00
json	Parse reals as string in JSON front-end	2017-09-26 14:37:03 +02:00
liberty	Also interpret '&' in liberty functions	2018-05-12 20:55:31 +02:00
verific	Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE	2018-05-24 18:13:38 +02:00
verilog	Support SystemVerilog `` extension for macros	2018-05-17 00:09:56 -04:00