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yosys/tests/arch/common
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diego 22f440506b Modifications of tests as per Eddie's request 2020-04-20 12:45:35 -05:00
..
dynamic_part_select Modifications of tests as per Eddie's request 2020-04-20 12:45:35 -05:00
memory_attributes Fixing compiler warning/issues. Moving test script to the correct place 2019-12-16 10:23:45 -06:00
add_sub.v Unify verilog style 2019-10-18 12:50:24 +02:00
adffs.v Unify verilog style 2019-10-18 12:50:24 +02:00
blockram.v ice40: add support for both 1364.1 and LSE RAM/ROM attributes. 2020-02-06 14:58:20 +00:00
blockrom.v ecp5: add support for both 1364.1 and LSE RAM/ROM attributes. 2020-02-06 16:52:51 +00:00
counter.v fixed error 2019-10-18 13:15:36 +02:00
dffs.v Unify verilog style 2019-10-18 12:50:24 +02:00
fsm.v Unify verilog style 2019-10-18 12:50:24 +02:00
latches.v Unify verilog style 2019-10-18 12:50:24 +02:00
logic.v Unify verilog style 2019-10-18 12:50:24 +02:00
lutram.v Rename memory tests to lutram, add more xilinx tests 2019-12-12 17:44:37 -08:00
mul.v Unify verilog style 2019-10-18 12:50:24 +02:00
mux.v Unify verilog style 2019-10-18 12:50:24 +02:00
shifter.v Unify verilog style 2019-10-18 12:50:24 +02:00
tribuf.v Unify verilog style 2019-10-18 12:50:24 +02:00