riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/backends
History
Clifford Wolf 1e6836933d Added modelsim support to autotest 2013-11-24 15:10:43 +01:00
..
autotest Added modelsim support to autotest 2013-11-24 15:10:43 +01:00
blif Added "top" attribute to mark top module in hierarchy 2013-11-24 05:03:43 +01:00
edif Added "top" attribute to mark top module in hierarchy 2013-11-24 05:03:43 +01:00
ilang Major improvements in mem2reg and added "init" sync rules 2013-11-21 13:49:00 +01:00
intersynth Renamed "placeholder" to "blackbox" 2013-11-22 15:01:12 +01:00
spice Added "top" attribute to mark top module in hierarchy 2013-11-24 05:03:43 +01:00
verilog Renamed "placeholder" to "blackbox" 2013-11-22 15:01:12 +01:00