yosys/passes
Zachary Snow c016f6a423 proc_rmdead: use explicit pattern set when there are no wildcards
If width of a case expression was large, explicit patterns could cause
the existing logic to take an extremely long time, or exhaust the
maximum size of the underlying set. For cases where all of the patterns
are fully defined and there are no constants in the case expression,
this change uses a simple set to track which patterns have been seen.
2021-07-29 20:55:59 -04:00
..
cmds rtlil: Make Process handling more uniform with Cell and Wire. 2021-07-12 00:47:34 +02:00
equiv Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
fsm Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
hierarchy Use new read_id_num helper function elsewhere in hierarchy.cc 2021-07-20 10:13:15 -04:00
memory Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
opt opt_lut: Allow more than one -dlogic per cell type. 2021-07-29 17:30:07 +02:00
pmgen Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
proc proc_rmdead: use explicit pattern set when there are no wildcards 2021-07-29 20:55:59 -04:00
sat memory: Introduce $meminit_v2 cell, with EN input. 2021-07-28 23:18:38 +02:00
techmap Fix deadname SVN links 2021-06-09 12:44:37 +02:00
tests Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00