yosys/passes
Clifford Wolf ab71bd0746 Updated ABC to rev e97a6e1d59b9 2014-02-12 08:35:42 +01:00
..
abc Updated ABC to rev e97a6e1d59b9 2014-02-12 08:35:42 +01:00
cmds Added delete {-input|-output|-port} 2014-02-09 10:03:26 +01:00
fsm Fixes in fsm detect/extract for better detection of non-fsm circuits 2013-12-06 12:53:20 +01:00
hierarchy Moved some passes to other source directories 2014-02-08 14:39:15 +01:00
memory Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect 2014-02-08 19:13:19 +01:00
opt Added opt -purge (frontend to opt_clean -purge) 2014-02-08 14:21:34 +01:00
proc Tiny cleanup in proc_mux.cc 2014-01-03 16:54:59 +01:00
sat Various improvements in expose command (added -sep and -cut) 2014-02-09 11:07:46 +01:00
techmap Moved some passes to other source directories 2014-02-08 14:39:15 +01:00