mirror of https://github.com/YosysHQ/yosys.git
17 lines
398 B
Plaintext
17 lines
398 B
Plaintext
read_verilog counter.v
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read_verilog -lib cmos_cells.v
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synth
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dfflibmap -liberty cmos_cells.lib
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abc -liberty cmos_cells.lib
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opt_clean
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stat -liberty cmos_cells.lib
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# http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib
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# dfflibmap -liberty osu025_stdcells.lib
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# abc -liberty osu025_stdcells.lib;;
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write_verilog synth.v
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write_spice synth.sp
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